holt integrated circuits www.holtic.com 1 HI-2130 single package mil-std-1553 / mil-std-1760 3.3v bc / mt / rt with integrated transformers ds2130 rev. b 01/13 features ? combined functionality of hi-6130 and hi-6131 in a single package with integrated transformers ? smallest footprint mil-std-1553 solution available (includes transformers) ? extended temperature range, -55oc to +125oc, with optional burn-in ? hermetically sealed die improves reliability and achieves msl 1 ? less expensive than traditional multi-chip modules ? do-254 certifable ? concurrent multi-terminal operation (bc, mt, 1 or 2 independent rts) ? two host interface options in one package: 16-bit parallel bus or 4-wire spi ? 64k bytes on-chip ram with error detection/ correction option ? autonomous terminal operation requires minimal host intervention ? shared mil-std-1553 bus interface reduces circuit complexity and circuit board area. ? fully programmable bus controller with 28 op code instruction set ? simple monitor terminal (smt) mode records commands and data separately, with 16-bit or 48-bit time tagging ? irig monitor terminal (imt) mode supports irig-106 chapter 10 packet format. complete irig-106 data packets including full packet headers and trailers can be generated ? independent time-tag counters for all terminals with 32-bit option for bus controller and 48-bit option for monitor terminal ? 64-word interrupt log buffer queues the most recent 32 interrupts. hardware-assisted interrupt decoding quickly identifes interrupt sources ? built-in self-test for protocol logic, digital signal paths and internal ram ? optional self-initialization at reset uses external serial eeprom ? two temperature ranges: -40 o c to +85 o c, or -55 o c to +125 o c general description the HI-2130 provides a 3.3v fully integrated interface between a host processor and a mil-std-1553 / mil-std-1760 bus. it combines the functionality of holts hi-6130 16-bit parallel bus interface and hi-6131 spi devices, integrating mil-std-1553 protocol logic, dual transceivers and dual transformers in a single compact 15 x 15mm package. the HI-2130 die is hermetically sealed in a ceramic substrate and dual transformers are mounted onto the same package. two package options are offered, namely bga and pga (see ordering information on page 6 ). the device includes the entire signal i/o set of hi-6130 and hi-6131, with the addition of a new input signal for selecting parallel bus or spi host interface. two pairs of transformer output signals connect directly to the mil-std-1553 bus a and bus b stubs. the part is available in industrial -40 o c to +85 o c, or extended, -55 o c to +125 o c temperature ranges. optional burn-in is available on the extended temperature range. refer to the hi-6130 datasheet for full functional description and operation. 64k byte shared ram external serial flash eeprom interface transceiver a transceiver b HI-2130 bc mt rt rt mil-std-1553 protocol & memory management transformers january 2013
holt integrated circuits 2 block diagram r t 1 message processor bc message processor mt message processor r t 2 message processor bus b manchester encoder bus b manchester decoder bus a manchester encoder bus a manchester decoder reset & initializatio n logi c memory and register access control address data control discret e signal inputs configuration option logic t est logi c busb busb txinhb txinha mclk ttclk internal clocks gnd vdd power test mode r t2ssf ackirq r t1ssf mr r t2a4-0 aut oen r t2ap eecopy bendi ramedc r t1lock mttclk r t1a4-0 r t1ap mtst off r t2lock r t1ena r t2ena bcena mtrun host interface ir q mtpkrdy ready active ce we re a0 w a it d15:0 a15:1 btype bwid wpol r t1mc8 r t2mc8 discret e signal output s sck mosi miso s e r d d a s t a d a o r t n o c l 64k static ram and registers s s e r d d a t a d a o r t n o c l serial peripheral interface (spi ) to eeprom optional serial eeprom (auto-config) s c e k c s e i s o m o s i m s e r d d a s t a d a o r t n o c l x t 3 5 5 1 w s d r o x r 3 5 5 1 w s d r o s e r d d a & s o r t n o c l o w d r s bctrig busa busa bus / spi HI-2130 hi-6130 / hi-6131 HI-2130
holt integrated circuits 3 pin diagram mtpkt rdy 1 3 2 4 6 5 8 7 9 11 10 1 3 2 4 6 5 8 7 9 11 10 a b c d e f g h j k l a b c d e f g h j k l ram edc data 14 data 11 data 9 data 4 rt1 ssf rt1 mc8 b type nirq bendi ac- tive nce data 12 data 10 auto en data 6 vdd ack irq wpol data 2 nbus a ready mode bc trig data 13 tx inha data 7 data 5 test data 1 data 0 nbus a rt2 mc8 miso data 15 mosi tx inhb data 8 data 3 mtst off dnc rt1 lock bus a gnd nwait sclk nre vdd gnd vdd vdd dnc bc ena bus a vdd nwe bus nspi mclk gnd vdd gnd gnd dnc vdd dnc gnd rt1 a2 rt1 a0 rt1 a1 vdd gnd vdd vdd dnc rt2 ena bus b mt run addr 0 rt1 ena addr 2 e mosi gnd ee copy rt2 a2 addr 14 rt2 a3 nbus b esck addr 1 addr 3 addr 4 addr 6 tt clk vdd rt2 ssf addr 15 addr 13 nbus b addr 11 addr 5 rt1 ap e miso addr 7 mtt clk addr 9 rt2 ap addr 12 rt2 a4 bwid rt2 lock nmr rt1 a3 rt1 a4 addr 8 necs addr 10 rt2 a0 dnc rt2 a1 bus b top view see hi-6130 datasheet for a full pin description. notes: a. dnc: do not connect. b. all balls denoted vdd must be connected to 3.3v dc power. c. all balls denoted gnd must be connected to circuit ground. d. bus/nspi (f10) selects 16-bit wide parallel bus or spi operation (see section selection of host interface on page 4 ). e. nce: the chip enable signal is shared between 16-bit parallel and spi host interfaces (spi slave select ). HI-2130
holt integrated circuits 4 operation refer to the hi-6130 datasheet for detailed operation and register description. selection of host interface the host interface is selected using the spi/ bus pin. ? bus/ spi pin set to logic 1: selects 16-bit parallel bus host interface ? bus/ spi pin reset to logic 0: selects spi host interface HI-2130
holt integrated circuits 5 package dimensions .500 (12.7) l k j h g f e d c b a 10x @ .050 (1.27) 1 2 3 4 5 6 7 8 9 10 11 .500 (12.7) 10x @ .050 (1.27) 121x ?.0338 +0.0020 ?0.0019 ?.012 c a a b m ?.006 c m bottom view dimensions in inch (mm) pin grid array (121pga) inches HI-2130 top view 0.590 (14.986) 0.590 (14.986) 121x @ .120 (3.048) 121x .011 (0.28) +.003 (0.076) ?.001 (0.025) .075 .008 (1.9 0.2) 0.220 (5.59) dimensions in inch (mm) bottomview a 1 2 3 4 5 6 7 8 9 10 11 b c d e f g h j k l 10 eq. sp. @ .050 (1.27) = 0.5 (12.7) .050 (1.27) 0.045 (1.143) 121x ? = 0.035 (0.89) ball grid array (121bga) HI-2130 top view 0.590 (14.986) 0.590 (14.986) 0.075 (1.905) 0.220 (5.59) HI-2130
holt integrated circuits 6 ordering information part number lead finish blank tin / lead (sn / pb) fnish, bga only f pb-free, rohs compliant part number temperature range flow burn in i -40 o c to +85 o c i no t -55 o c to +125 o c t no part number package description cp 121 pin grid array - pga (121pga), (pb-free, rohs compliant) cb 121 ball grid array - bga (121bga), non-collapsing solder balls hi - 2130 cx x f HI-2130
holt integrated circuits 7 revision history revision date description of change ds2130, rev. new 09/14/12 initial release. rev. a 11/14/12 corrected typos in pin diagram. updated package drawings for new thickness. updated ordering information table. rev. b 01/22/13 remove lga package option. HI-2130
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